A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications
نویسندگان
چکیده
A 4096×2160p multiview video encoder chip is implemented on a 3.95mm×2.90mm die with 90nm CMOS technology. A view-parallel macroblock-interleaved scheduling with 8stage macroblock pipelined architecture achieves 212Mpixels/s throughput, which is 3.4× to 7.7× better than the state-of-the-art encoder chips. In addition, 94% on-chip SRAM area and 79% external system memory bandwidth are saved.
منابع مشابه
A 212 MPixels/s 4096 ˟ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications
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